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this is information on a product in full production. october 2013 docid025389 rev 2 1/24 m41t01 low-power serial real-time clock (rtc) with built-in battery switchover circuit datasheet - production data features ? 2.0 to 5.5 v clock operating voltage ? counters for seconds, minutes, hours, day, date, month, years, and century ? software clock calibration ? automatic switchover and deselect circuitry ? ultra-low battery supply current of 800 na ? low operating current of 300 a ? battery and capacitor backup ? battery backup not recommended for 3.0 v applications (capacitor backup only) ? operating temperature of ?40 to 85 c ? automatic leap year compensation description the m41t01 is a low-power serial real-time clock (rtc). the built-in 32.768 khz oscillator circuit works with an external crystal and does not need any load capacitors. the m41t01 clock has a built-in power sense circuit which detects power failures and automatically switches to the battery supply during power failures. eight bytes of the ram are used for the clock/calendar function and are configured in binary-coded decimal (bcd) format. addresses and data are transferred serially via a two-line bidirectional bus. the built-in address register is incremented automatically after each write or read data byte. the energy needed to sustain the ram and clock operations can be supplied from a small lithium coin cell. typical data retention time is in excess of 5 years with a 50 ma/h 3 v lithium cell. the m41t01 is supplied in an 8-lead plastic small outline package. 8 1 so8 www.st.com
contents m41t01 2/24 docid025389 rev 2 contents 1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
docid025389 rev 2 3/24 m41t01 list of tables 24 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. so8 ? 8-lead plastic small outline package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 21 table 11. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 12. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
list of figures m41t01 4/24 docid025389 rev 2 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 6. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. alternate read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 11. clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. ac testing input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 13. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. so8 ? 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
docid025389 rev 2 5/24 m41t01 device overview 24 1 device overview figure 1. logic diagram figure 2. soic connections table 1. signal names osci oscillator input ocso oscillator output ft/out frequency test / output driver (open drain) sda serial data address input / output scl serial clock v bat battery supply voltage v cc supply voltage v ss ground ai07068b osci v cc m41t01 v ss scl osco sda ft/out v bat 1 sda v ss scl ft/out osco osci v cc v bat ai07069b m41t01 2 3 4 8 7 6 5
device overview m41t01 6/24 docid025389 rev 2 figure 3. block diagram ai07070b seconds oscillator 32.768 khz voltage sense and switch circuitry serial bus interface divider control logic address register minutes century/hours day date month year control osci osco ft/out v cc v ss v bat scl sda 1 hz
docid025389 rev 2 7/24 m41t01 operation 24 2 operation the m41t01 clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 8 bytes contained in the device can then be accessed sequentially in the following order: 1. seconds register 2. minutes register 3. century/hours register 4. day register 5. date register 6. month register 7. years register 8. control register the m41t01 clock continually monitors v cc for an out of tolerance condition. should v cc fall below v so , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. when v cc falls below v so , the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. upon power-up, the device switches from battery to v cc at v so and recognizes inputs. 2.1 2-wire bus characteristics this bus is intended for communication between different ics. it consists of two lines: one bi-directional for data signals (sda) and one for clock signals (scl). both the sda and the scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: ? bus not busy both data and clock lines remain high. ? start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condition. ? stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition.
operation m41t01 8/24 docid025389 rev 2 ? data valid the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal (see figure 4 ). the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition, a device that gives out a message is called ?transmitter?, the receiving device that gets the message is called ?receiver?. the device that controls the message is called ?master?. the devices that are controlled by the master are called ?slaves?. figure 4. serial bus data transfer sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition
docid025389 rev 2 9/24 m41t01 operation 24 ? acknowledge each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse (see figure 5 ). a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case, the transmitter must leave the data line high to enable the master to generate the stop condition. figure 5. acknowledgement sequence ai00601 data output by receiver data output by transmitter sclk from master start clock pulse for acknowledgement 12 89 msb lsb
operation m41t01 10/24 docid025389 rev 2 2.2 read mode in this mode, the master reads the m41t01 slave after setting the slave address (see figure 6 ). following the write mode control bit (r/ w = 0) and the acknowledge bit, the word address an is written to the on-chip address pointer. next the start condition and slave address are repeated, followed by the read mode control bit (r/ w = 1). at this point, the master transmitter becomes the master receiver. the data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge bit. the m41t01 slave transmitter will now place the data byte at address a n+1 on the bus. the master receiver reads and acknowledges the new byte and the address pointer is incremented to a n+2 . this cycle of reading consecutive addresses will continue until the master receiver sends a stop condition to the slave transmitter. an alternate read mode may also be implemented, whereby the master reads the m41t01 slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 7 on page 11 ). figure 6. slave address location ai00602 r/w slave address start a 01000 11 msb lsb
docid025389 rev 2 11/24 m41t01 operation 24 figure 7. read mode sequence figure 8. alternate read mode sequence ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address
operation m41t01 12/24 docid025389 rev 2 2.3 write mode in this mode the master transmitter transmits to the m41t01 slave receiver. bus protocol is shown in figure 9 . following the start condition and slave address, a logic '0' (r/ w = 0) is placed on the bus and indicates to the addressed device that word address an will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowledge clock. the m41t01 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see figure 6 on page 10 ). 2.4 data retention mode with valid v cc applied, the m41t01 can be accessed as described above with read or write cycles. should the supply voltage decay, the m41t01 will automatically deselect, write protecting itself when v cc falls (see figure 13 on page 20 ). figure 9. write mode sequence ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
docid025389 rev 2 13/24 m41t01 clock operation 24 3 clock operation the eight byte clock register (see table 2 on page 14 ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. seconds, minutes, and hours are contained within the first three registers. bits d6 and d7 of clock register 2 (hours register) contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0', cb will not toggle. bits d0 through d2 of register 3 contain the day (day of week). registers 4, 5 and 6 contain the date (day of month), month and years. the final register is the control register (this is described in section 3.1: clock calibration ). bit d7 of register 0 contains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. when reset to a '0' the oscillator restarts within one second. note: in order to guarantee oscillator startup after the initial power-up, set the st bit to a '1,' then reset this bit to a '0.' this sequence enables a ?kick start? circuit which aids the oscillator start-up during worst case conditions of voltage and temperature. the seven clock registers may be read one byte at a time, or in a sequential block. the control register (address location 7) may be accessed independently. a provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. if a clock address is being read, an update of the clock registers will be delayed by 250 ms to allow the read to be completed before the update occurs. this will prevent a transition of data during the read. note: this 250 ms delay affects only the clock register update and does not alter the actual clock time.
clock operation m41t01 14/24 docid025389 rev 2 note: s = sign bit ft = frequency test bit st = stop bit out = output level x = don?t care ceb = century enable bit cb = century bit note: 1 when ceb is set to '1', cb will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). when ceb is set to '0', cb will not toggle. table 2. register map addr data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 0 st 10 seconds seconds seconds 00-59 1 x 10 minutes minutes minutes 00-59 2 ceb (1) cb 10 hours hours century/hours 0-1/00-23 3x xxxx day day 01-07 4 x x 10 date date date 01-31 5 x x x 10 m. month month 01-12 6 10 years years year 00-99 7 out ft s calibration control
docid025389 rev 2 15/24 m41t01 clock operation 24 3.1 clock calibration the m41t01 is driven by a quartz controlled oscillator with a nominal frequency of 32,768 hz. the devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25 c, which equates to about 1.53 minutes per month. with the calibration bits properly set, the accuracy of each m41t01 improves to better than 2 ppm at 25c. the oscillation rate of any crystal changes with temperature (see figure 10 on page 16 ). most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. the m41t01 design, however, employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in figure 11 on page 16 . the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits (d4-d0) in the control register (addr 7). this byte can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. assuming that the oscillator is in fact running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ? 2.75 minutes per month. two methods are available for ascertaining how much calibration a given m41t01 may require. the first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. all the designer has to do is provide a simple utility that accessed the calibration byte. the second approach is better suited to a manufacturing environment, and involves the use of some test equipment. when the frequency test (ft) bit, the seventh-most significant bit in the control register, is set to a '1', and the oscillator is running at 32,768 hz, the ft/out pin of the device will toggle at 512 hz. any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.01024 hz would indicate a +20 ppm oscillator frequency error, requiring a ?10(xx001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency.
clock operation m41t01 16/24 docid025389 rev 2 figure 10. crystal accuracy across temperature figure 11. clock calibration 3.2 output driver pin when the ft bit is set, the ft/out pin provides a nominal 512 hz frequency output used for calibration purposes (see section 3.1 ). when the ft bit is set to zero, the ft/out pin becomes an output driver that reflects the contents of the out bit (d7 bit of register 7, see table 2 ). if the out bit is zero, then the ft/out pin will be driven low, if the out bit is one, then the ft/out pin will be driven high. the out bit can be written through the 2-wire bus port. note: the ft/out pin is open drain which requires an external pull-up resistor. 3.3 initial power-on defaults upon initial application of power to the device, the ft bit will be set to a '0' and the out bit will be set to a '1'. all other register bits will initially power on in a random state. ai00999b ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 f = k x (t ?t o ) 2 k = ?0.036 ppm/ c 2 0.006 ppm/ c 2 t o = 25 c 5 c f ai00594b normal positive calibration negative calibration
docid025389 rev 2 17/24 m41t01 maximum rating 24 4 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. . caution: negative undershoots below ?0.3 v are not allowed on any pin while in the battery backup mode. table 3. absolute maximum ratings symbol parameter value units t a ambient operating temperature ?40 to 85 c t stg (1)(2) 1. for so package, standard (snpb) lead finish: reflow at peak temperature of 225c (the time above 220 c must not exceed 20 seconds) 2. for so package, lead-free (pb-free) lead finish: reflow at peak temperature of 260c (the time above 255 c must not exceed 30 seconds) storage temperature (v cc off, oscillator off) ?55 to 125 c v io input or output voltages ?0.3 to 7 v v cc supply voltage ?0.3 to 7 v i o output current 20 ma p d power dissipation 0.25 w
dc and ac parameters m41t01 18/24 docid025389 rev 2 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. note: output hi-z is defined as the point where data is no longer driven. figure 12. ac testing input/output waveform 1. effective capacitance measured with power supply at 5 v; sampled only, not 100% tested. 2. at 25 c, f = 1 mhz. 3. outputs deselected. table 4. operating and ac measurement conditions parameter m41t01 unit supply voltage (v cc ) 2.0 to 5.5 v ambient operating temperature (t a ) ?40 to 85 c load capacitance (c l ) 100 pf input rise and fall times ? 5ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing ref. voltages 0.3v cc to 0.7v cc v table 5. capacitance symbol parameter (1,2) min max unit c in input capacitance (scl) 7 pf c out (3) output capacitance (sda, ft/out) 10 pf t lp low-pass filter input time constant (sda and scl) 250 1000 ns ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc
docid025389 rev 2 19/24 m41t01 dc and ac parameters 24 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 2.0 to 5.5 v (except where noted). 2. stmicroelectronics recommends the rayovac br1225 or br1632 (or equivalent) as the battery supply. 3. after switchover (v so ), v bat (min) can be 2.0 v for crystal with r s = 40 k ? . 4. for rechargeable back-up, v bat (max) may be considered v cc . table 6. dc characteristics symbol parameter test condition (1) min typ max unit i li input leakage current 0 v ? v in ? v cc 1 a i lo output leakage current 0 v ? v out ? v cc 1 a i cc1 supply current switch frequency = 100 khz 300 a i cc2 supply current (standby) scl, sda = v cc ? 0.3 v 70 a v il input low voltage ?0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v pull-up supply voltage (open drain) ft/out 5.5 v v bat (2) battery supply voltage 2.5 (3) 3 3.5 (4) v i bat battery supply current t a = 25 c, v cc = 0 v, oscillator on, v bat = 3 v 0.8 1 a table 7. crystal electrical characteristics symbol parameter (1)(2) min typ max unit f o resonant frequency 32.768 khz r s series resistance 60 k ? c l load capacitance 12.5 pf 1. these values are externally supplied. stmicroelectronics recommends the kds dt-38: 1ta/1tc252e127, tuning fork type (thru-hole) or the dmx-26s: 1tjs125fh2a212, (smd) quartz crystal for industrial temperature operations. 2. load capacitors are integrated within the m41t01. circuit board layout considerations for the 32.768 khz crystal of minimum trace lengths and isolation from rf generating signals should be taken into account.
dc and ac parameters m41t01 20/24 docid025389 rev 2 figure 13. power down/up mode ac waveforms 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 2.0 to 5.5 v (except where noted). 2. v cc fall time should not exceed 5 mv/ s. 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 2.0 to 5.5 v (except where noted). 2. all voltages referenced to v ss . 3. in 3.3 v application, if initial battery voltage is ? 3.4 v, it may be necessary to reduce battery voltage (i.e., through wave soldering the battery) in order to avoid inadvertent switchover/deselection for v cc ? 10% operation. 4. switchover and deselect point. table 8. power down/up ac characteristics symbol parameter (1) min max unit t pd scl and sda at v ih before power-down 0 ns t rec (2) scl and sda at v ih after power-up 10 s table 9. power down/up trip points dc characteristics symbol parameter (1,2) min typ max (3) unit symbol parameter (1,2) min typ max (3) unit v so (4) battery backup switchover voltage v bat ? 0.80 v bat ? 0.50 v bat ? 0.30 v ai00596 v cc trec tpd v so sda scl don't care
docid025389 rev 2 21/24 m41t01 package mechanical information 24 6 package mechanical information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 14. so8 ? 8-lead plastic small package outline note: drawing is not to scale. so-a e n cp b e a d c l a1 1 h h x 45? table 10. so8 ? 8-lead plastic small outline package mechanical data sym mm inches typ min max typ min max a ? 1.35 1.75 ? 0.053 0.069 a1 ? 0.10 0.25 ? 0.004 0.010 b ? 0.33 0.51 ? 0.013 0.020 c ? 0.19 0.25 ? 0.007 0.010 d ? 4.80 5.00 ? 0.189 0.197 e ? 3.80 4.00 ? 0.150 0.157 e 1.27 ? ? 0.050 ? ? h ? 5.80 6.20 ? 0.228 0.244 h ? 0.25 0.50 ? 0.010 0.020 l ? 0.40 0.90 ? 0.016 0.035 ? ? 0 8 ? 0 8 n8 8 cp ? ? 0.10 ? ? 0.004
part numbering m41t01 22/24 docid025389 rev 2 7 part numbering table 11. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m41t 01 m 6 f device type m41t supply voltage and write protect voltage 01 = v cc = 2.0 to 5.5 v package m = so8 (150 mils width) temperature range 6 = ?40 to 85c shipping method f = ecopack ? package, tape & reel
docid025389 rev 2 23/24 m41t01 revision history 24 8 revision history table 12. document revision history date revision changes 01-may-2006 1 initial release 21-oct-2013 2 updated title, features , description updated footnotes 1 and 2 of table 3: absolute maximum ratings updated section 3.2: output driver pin updated footnote 1 of table 7: crystal electrical characteristics added ecopack ? paragraph to section 6: package mechanical information updated table 11: ordering information scheme
m41t01 24/24 docid025389 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. a ll st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industr y domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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